Embodiments of the present invention relate in general to an out-of-order (OoO) processor and more specifically to hazard detection of out-of-order execution of load and store instructions without using real addresses.
In an OoO processor, an instruction sequencing unit (ISU) dispatches instructions to various issue queues, renames registers in support of OoO execution, issues instructions from the various issue queues to the execution pipelines, completes executed instructions, and handles exception conditions. Register renaming is typically performed by mapper logic in the ISU before the instructions are placed in their respective issue queues. The ISU includes one or more issue queues that contain dependency matrices for tracking dependencies between instructions. A dependency matrix typically includes one row and one column for each instruction in the issue queue.
In the domain of central processing unit (CPU) design, and particularly for OoO processors, hazards pose technical challenges with the instruction pipeline in the CPU microarchitectures when a next instruction cannot execute in the following clock cycle, because of potentially leading to incorrect computation results. Typical types of hazards include data hazards, structural hazards, and control flow hazards (branching hazards). Data hazards occur when instructions that exhibit data dependence modify data in different stages of a pipeline, for example read after write (RAW), write after read (WAR), and write after write (WAW). A structural hazard occurs when a part of the processor's hardware is needed by two or more instructions at the same time, for example a memory unit being accessed both in the fetch stage where an instruction is retrieved from memory, and the memory stage where data is written and/or read from memory. Further, branching hazards (also termed control hazards) occur with branches in the computer program being executed by the processor.